Design And Reuse SoC News Alert

December 28, 2004

Michael,
Welcome to issue of December 28, 2004 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

SPONSORED BY: eASIC, Corp.

NRE-free Structured ASIC

ASIC-like unit-cost, power and performance

FPGA-like ease of design (SRAM-LUT)

Flexible exchange between logic and distributed memory

No minimum volume required

Turnaround: < 2 weeks

Built-in clock tree, BIST, scan chain and power distribution

Easy post-fabrication debug - LUT reload

Variety of configurable I/Os

Embedded 8051 microcontroller

MPEG-2 to H.264 Transcoder from Ittiam System

Silicon-proven IP for AES encryption and decryption from SafeNet, Inc.

20-bit 93dB Dynamic Range 48kHz Sampling Frequency Stereo Audio DAC with Mixing Line Input from ChipIdea Microelectronics

ATCA PICMG 3.0 Reference Design from Avnet Electronics Marketing

Entering the Backplane Fast Lane

IP/SOC PRODUCTS

Faraday announces the launching of the world smallest programmable PLL-miniPLL

BUSINESS

ARM shares slip as Artisan acquisition completed

ARM Announces Completion of Acquisition of Artisan Components, Inc.

Artisan Components, Inc. Announces Stockholder Approval of Merger with ARM Holdings plc

ARM Announces Results of Extraordinary General Meeting

MPEG LA Announces Plan for ATSC Patent License

MPEG LA Announces Plan for DVB-H Patent License

TAEUS International Corporation Launches Web-Based Intellectual Property Auction

PEOPLE

Heard on the Beat: new chairman named at FSA

Arteris, a start-up developing Network on Chip (NoC) Intellectual Property, names Philippe Geyres to its Board of Directors

FOUNDRIES

Chinese foundry ASMC to move ahead with IPO

SMIC reduces Q4 guidance, cites industry slowdown

FPGA/CPLD

Altera Ships Industry's Highest-Density FPGAs Qualified for Production

Altera Stratix Devices Deliver High Performance for Maranti's CoreSTOR Network Storage Controller

EDA

Synopsys shift caused EDA decline, analysts say

SPONSORED BY: TEMENTO SYSTEMS

Temento Systems, innovative provider of test, debug and verify solutions for FPGA and Hardware Platforms now offer two Edition of its DiaLite On-Chip Instrumentation tool. The new HDL Fault Finder IP included into the Power Edge Edition allows accurate monitoring and display of logic events contained into your HDL code. Designers have now the possibility to insert Watchpoints and Breakpoints on the instruments and into the code, and make it run concurrently to the instrumentation.

Click here to know more about Temento

D&R Silicon IP / SoC Catalog :
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A catalog of Hardware dependent Software (HdS) ranging from embedded OS to Communication Stacks and Application Software

D&R Verification IP Catalog :
Speed up your verification of protocol-centric designs by finding the specific Verification IP you need (already more than 100 products listed !!!)

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